- Category: Computer Architecture
- Location: Olin College of Engineering
- Project date: December 2022
- Project URL: https://github.com/mstopyra/FPGA_SIGDEL_DAC
Conceived, architected, and meticulously implemented a sigma-delta digital-to-analog converter (DAC) within the SystemVerilog framework. This project involved the comprehensive design of a sophisticated circuit that utilized the sigma-delta modulation technique to achieve high precision in digital-to-analog conversion. The development process encompassed a detailed exploration of the DAC's architecture, the selection of appropriate components, and the intricacies of the SystemVerilog programming language to ensure optimal performance and accuracy in signal conversion. This endeavor demanded a thorough understanding of digital signal processing principles and a keen attention to detail to bring the DAC to fruition successfully.